1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to an SRAM.
2. Description of the Related Art
As the demand has increased for increasing the capacity and speed of an SRAM, transistors that form SRAM cells have also increasingly advanced in fine structure and speed. As a result, leakage currents that occur in bit lines have increased more and more. The leakage current is caused by a leakage current of an off-state transfer gate transistor in each SRAM cell. If, therefore, the number of SRAM cells connected to one bit line increases, then the total amount of leakage current that occurs in bit lines will increase to a level that cannot be neglected, causing a problem of the occurrence of data read errors. In particular, in a configuration in which only one of the complementary bit lines is used to read data, when the same potential as the precharge potential is read out onto the bit line to which a data read circuit is connected, data must be compensated for by the precharge potential on the bit line that is set at a floating state. This further increases the possibility of data read errors due to the leakage currents.
For precharging, there is a conventional technique in which a precharge circuit that doubles as a write driver is used to precharge a bit line selected at the time of reading from the SRAM (see, for example, Japanese Unexamined Patent Application Disclosure No. 6-195977).
In addition, there is another conventional technique in which a precharge circuit is provided which has a function of, at precharge time, selectively restoring the potential on a bit line connected to an SRAM cell whose discharged condition has been checked in advance (see, for example, U.S. Pat. No. 6,064,616).
With the former technique, however, it is impossible to cope with a drop in the potential on the bit lines due to leakage currents from many SRAM cells after precharging is performed to the bit lines, causing read errors to occur.
With the latter technique, on the other hand, it is possible to cope with a drop in the potential on the bit line connected to an SRAM cell in question; however, as with the former technique, it is impossible to cope with a drop in the potential on the bit lines due to leakage currents from many SRAM cells after precharging, likewise causing read errors to occur.
With the conventional memory devices, when data the potential of which is the same as the precharge potential is read from an SRAM cell onto its associated bit line, the transfer gate transistor provided in the corresponding memory cell is turned off, making it impossible to supply or compensate charges to that bit line. For this reason, the presence of a leakage current from a precharged bit line at data read time causes the potential on it to drop and causes the data read error.